A stacked structure is known in which two printed wiring boards are bonded to each other with a prepreg sandwiched between them. Electrodes are provided on the printed wiring boards, and conductive vias corresponding to the electrodes are provided to the prepreg. That is, the prepreg includes conductive vias.
Recently, short circuit easily occurs between conductive vias accompanying micro-fabrication. The short circuit between conductive vias leads to short circuit between electrodes, and since the short circuit between electrodes cannot be repaired, a stacked structure in which such short circuit occurred is discarded. Therefore, occurrence of short circuit leads to decrease in yield.
Patent Literature 1: Japanese Laid-open Patent Publication No. 2006-49412
Patent Literature 2: Japanese Laid-open Patent Publication No. 2008-294246
Patent Literature 3: Japanese Laid-open Patent Publication No. 2011-96900
Patent Literature 4: Japanese Patent No. 2603053